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Session Track: General
Light Lunch Buffett
  • Speaker:  
Time: Monday, May 06, 12:00 - 13:30, Room: Designer Expo
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Session Description: Light Lunch Buffett

Session Track: Academic
[AC01] Updated Cadence 2019 Portfolio Available for European Academics via Europractice (STFC)
  • Speaker: Bryony Howard, Science and Technology Facilities Council 
Time: Monday, May 06, 13:30 - 14:00, Room: Pilsensee
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Session Description: Updated Cadence 2019 Portfolio Available for European Academics via Europractice

Bryony Howard Bio:
Session Track: Automotive and IP Solutions
[ASIP01] Automotive System Enablement (Cadence)
  • Speaker: Robert Schweiger, Director, Automotive Solutions, Cadence 
Time: Monday, May 06, 13:30 - 14:00, Room: Schliersee
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Session Description: While some automakers already developing systems that are targeting level 4 automated driving which means “eyes off”, most companies are still trying hard to get level 3 automated cars in production. Radar, Lidar and Camera are the key sensors to enable level 3-5 autonomous driving up to 130 km/h. However, these sensors need to be significantly improved in terms of resolution, safety, power consumption, form factor and cost. Hence, future cars will be equipped with sensor clusters, more computing power, AI-based systems, car-to-car communication technology, high-bandwidth Ethernet networks, and integrated cockpits. All these new technologies create new challenges for automotive suppliers, such as more complex electronic systems which require to integrate more functionality on a chip, rather than on a PCB to provide the performance, safety and reliability in a small form factor device. As a result, suppliers will need to design a new class of high-performance System-on-Chip (SoC) and/or System-in-Package (SiP) to process all sensor data and fuse them together to enable vehicles to become “aware” of their surroundings. Cadence's automotive solutions can help you to enable such highly integrated systems that can make cars safer and more reliable. This talk provides an overview on automotive SoC and System enablement with a focus on Sensors and Advanced Driver Assist Systems (ADAS).

Robert Schweiger Bio: Robert Schweiger is Director Automotive Solutions at Cadence Design Systems. In this worldwide role he is responsible for driving the development of Automotive Solutions across all Cadence product lines covering tools, IP and services. Robert joined Cadence in 2002 and is based in Munich/Germany. Before his automotive assignment in 2012 he was responsible for the Virtuoso Custom IC product line in Europe. Before joining Cadence he held various management and engineering positions at Avant! Corporation and Analogy. Robert received his master degree in electrical engineering from the Munich University of Applied Sciences.
Session Track: Custom IC Design and Verification
[CUS01] PVS Voltage Aware DRC Using PVL Tcl DFM PROPERTY Advance Commands (TowerJazz)
  • Speaker: Ofer Tamir, Senior Director, CAD, Design Enablement & Support, TowerJazz 
Time: Monday, May 06, 13:30 - 14:00, Room: Ammersee I
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Session Description: As high voltage metal space requirements in larger than low voltage, some times over 3 times larger, one required to draw layout according to the voltage level and accommodate voltage level spacing. As standard DRC cannot accommodate voltage rules, the common way is to draw all metal spacing as high voltage and as such to make sure the design is always clean – that is, in some cases huge area penalty. In TowerJazz PM technology we have 2 DRC level complexity solution for those checks, each has it’s benefit and drawbacks. The 2 are: support layer DRC, voltage value and dfm property DRC for voltage difference – other solution is to use simulation values BUT it is good for small design and not full chip. In the presentation we will present the 2 different ways , advantages and disadvantages as well as we will show real design example with the 3 difference ways. The voltage difference use a propagation method of the DFM voltage property and then run special DRC per real voltage difference. Using PVS pvtcl language and DFM PROPERY command allow us to implement real voltage space rule. We will present the method, code and how we implement that sophisticate checks using PVS

Ofer Tamir Bio:
Session Track: Full-Flow Digital Design and Signoff
[DSG01] The Challenge of Designing a “First-Time-Right” Wi-Fi HaLow Baseband in Less than Six Months (Methods2Business)
  • Speaker: Stefan Stanic, ASIC Hardware IP design engineer, Methods2Business 
Time: Monday, May 06, 13:30 - 14:00, Room: Ammersee II
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Session Description: Developing a new IP for a completely new technology is always a challenge, particularly when the IP is part of a complex embedded system that needs to work as a total to prove the correctness of the IP. Building the IP for a new Wi-Fi Standard which is not on the market yet, makes it even more challenging. It requires an approach that not only furnishes fully integrated, high quality System-on-Chip solutions that can enter the market quickly, but also easy to customize IP blocks for dealing with late spec changes or for offering customers the ability to differentiate their end products. Other than that, there is the ever-present requirement that the IP should be available as soon as possible. The question is, what design methodology will allow us to efficiently complete this challenge? In this presentation, we will show you how Methods2Business unique SystemC-based design methodology greatly helped us in developing, verifying and testing a complete family of fully integrated MAC and baseband IPs for the new Wi-Fi standard for IoT, called Wi-Fi HaLow™. The focus of the presentation will be on how we managed to build a completely functional Wi-Fi HaLow™ 802.11ah compliant BASEBAND IP in just 6 months. The power and efficiency of this methodology is based on a unique SystemC-based design methodology enabling High-Level Synthesis for fast design and implementation of the hardware IPs, virtual platforms for debugging the full hardware and software of the Wi-Fi HaLow IP products in a system context, solid UVM en formal IP verification for ensuring the functional correctness of the IP, and a smooth trajectory to the essential FPGA prototyping environment for wireless (over the air) testing of the fully integrated IP. The methodology could be implemented thanks to Cadence EDA tools. Furthermore, this presentation will show an example of the M2B Wi-Fi HaLow™ 802.11ah MAC and BASEBAND products as IP cores developed and improved using the M2B methodology.

Stefan Stanic Bio: Stefan Stanić was born on August 22th 1994 in Novi Sad, Serbia. He holds a master degree in electrical and computer engineering from the University of Novi Sad. Stefan started his career at Methods2Business as a master thesis student applying hardware design knowledge in a SystemC-based HLS design flow. After his graduation, he went on to design CCMP crypto-core IP used in M2B Wi-Fi HaLow™ 802.11ah MAC solution and played a key role in the design and implementation of a Wi-Fi HaLow™ 802.11ah BASEBAND IP. His focus today is to further enhance his expertise in high-level synthesis for building the next generations of Wi-Fi HaLow™ IP products.
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